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SoC FPGA/FPGA Design Solution

Offering advanced FPGA development with a wide range of solutions, based on expertise achievements and technology development capabilities from major partners

Virtual ASSP

Virtual ASSP to further deepen the merits of ASIC and FPGA. In virtual ASSP, the disadvantage of commercial products, that it cannot be customized has been improved and flexible high-function chip that can incorporate original functions are implemented at a low price.

Reliable FPGA design with DSN partner registration

The Design Solution Network (DSN) is a global ecosystem partner program that supports the development of Intel® FPGAs, SoCs, and Enpirion semiconductor devices. We have been registered as a partner since 2014, based on a comprehensive evaluation by Intel, about our FPGA development results and efforts, expertise, and technology development capabilities we have built up until now.

Merits of DSN

1. The best possible solution is proposed.

By using technology network including Intel (earlier Altera) agency, high quality with less design time can be implemented.

2. Reduce development costs.

By providing Intel products (IP etc) to partner companies, development costs can be reduced (no license fee needed).

We can respond to various solutions through Intel’s broad marketing and sales channels. We provide all necessary materials including technical documentation and high quality customer support from Intel to partners.

We propose reliable design and high quality development required by customer companies by reducing the time, cost, and risk of product development by utilizing the merits of DNS, Intel’s products, know-how of NDR and Solutions provided by technology.

It is possible to implement reliable design development at low cost due to the strength of the world’s leading companies, partner program with Intel, and with the DNS membership.

High quality FPGA design with LINT

Normally, we check important caution points based on the advices and reviews of experienced engineers. However, we introduced LINT TOOL to FPGA design to improve the quality. We have made it possible to design high-quality FPGA with higher accuracy, such as improving the readability of code and mentoring ability by unifying the design quality level, identifying defective factors and so on.

Risks in FPGA design (Difficult to detect the defects and identify their causes after release)

Although in CPLD, schematic entry and asynchronous circuit were also possible, FPGA is based on synchronous circuit and language entry. However, the language entry has lowered the design entry hurdles, so we sometimes see an HDL that works “only” in logic simulation without considering the characteristics of the FPGA. In particular, if an asynchronous signal or a signal processing between different types of clocks fails, a product that includes the reproducibility of “it will always occur once every few days” and the problem that uses a large number of man-hours for identification might be produced.